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When designing a zkVM, choosing the right instruction set architecture (ISA) is foundational. While most new zkVM projects default to RISC-V due to its simplicity and growing ecosystem, ZKM deliberately took a more difficult route: building on MIPS32r2. This decision wasn’t about novelty - it was about choosing the best tool for verifiable computation at scale. MIPS32r2’s complexity may introduce engineering overhead, but we determined that its architectural advantages make it a superior fit for efficient zkVM design.
MIPS32r2 includes instructions like MOVZ, MOVN, and MADDU that allow complex logic to be encoded in fewer steps. This results in shorter programs and smaller execution traces. In contrast, RISC-V’s RV32I base set is intentionally minimalist. Expressing the same logic often requires multiple instructions, leading to bloat in both code and trace length.
Both ISAs use a fixed 32-bit instruction format. However, MIPS32r2 maintains this consistency across its instruction set, making encoding and decoding simpler. RISC-V starts with a clean 32-bit base, but real-world use often requires extensions (like M, A, F), introducing variability and implementation divergence.
MIPS32r2 provides built-in support for conditional execution through instructions like MOVZ and JAL, allowing efficient branching and function calls. RISC-V achieves similar behavior through sequences of simpler instructions, increasing the number of steps and introducing more surface area for circuit constraints.
MIPS32r2 has been standardized and battle-tested across decades of hardware and embedded systems. It has a fixed specification, making it stable for long-term zkVM integration. RISC-V, while gaining adoption quickly, is newer and still evolving - leading to fragmentation across implementations and toolchains.
The dense instruction format of MIPS means fewer operations are needed to perform the same computation. This directly reduces the length of execution traces and the number of constraints needed in a ZK circuit. With RISC-V, the increased number of steps translates to longer traces and more constraints to prove.
MIPS is not theoretical - it powers systems like Optimism’s fraud proof VM and has a long history of deployment in critical software. While RISC-V has early traction in zkRollups, its deployment across security-critical infrastructure is still maturing and fragmented.
Denser instructions in MIPS32r2 lead to fewer trace rows, reducing the overall proving cost. RISC-V programs often require more steps for equivalent logic, increasing the number of rows that must be committed and verified in the zero-knowledge proof.
While each MIPS instruction may carry more individual circuit cost due to its complexity, the total number of instructions per program is lower. This results in lower cumulative overhead. RISC-V’s simpler opcodes require composing many operations to express high-level logic, which increases the total circuit area needed to represent a program.
Choosing MIPS32r2 was not the easy path, but it was the path that made sense for scaling verifiable computation. ZKM made the harder engineering decision so that developers building on zkMIPS inherit a more performant, consistent, and scalable foundation for zk execution.
Subscribe to the ZKM Blog to stay updated with the latest research by ZKM. If you have any questions about the article, you can contact the ZKM team on discord: discord.com/zkm
When designing a zkVM, choosing the right instruction set architecture (ISA) is foundational. While most new zkVM projects default to RISC-V due to its simplicity and growing ecosystem, ZKM deliberately took a more difficult route: building on MIPS32r2. This decision wasn’t about novelty - it was about choosing the best tool for verifiable computation at scale. MIPS32r2’s complexity may introduce engineering overhead, but we determined that its architectural advantages make it a superior fit for efficient zkVM design.
MIPS32r2 includes instructions like MOVZ, MOVN, and MADDU that allow complex logic to be encoded in fewer steps. This results in shorter programs and smaller execution traces. In contrast, RISC-V’s RV32I base set is intentionally minimalist. Expressing the same logic often requires multiple instructions, leading to bloat in both code and trace length.
Both ISAs use a fixed 32-bit instruction format. However, MIPS32r2 maintains this consistency across its instruction set, making encoding and decoding simpler. RISC-V starts with a clean 32-bit base, but real-world use often requires extensions (like M, A, F), introducing variability and implementation divergence.
MIPS32r2 provides built-in support for conditional execution through instructions like MOVZ and JAL, allowing efficient branching and function calls. RISC-V achieves similar behavior through sequences of simpler instructions, increasing the number of steps and introducing more surface area for circuit constraints.
MIPS32r2 has been standardized and battle-tested across decades of hardware and embedded systems. It has a fixed specification, making it stable for long-term zkVM integration. RISC-V, while gaining adoption quickly, is newer and still evolving - leading to fragmentation across implementations and toolchains.
The dense instruction format of MIPS means fewer operations are needed to perform the same computation. This directly reduces the length of execution traces and the number of constraints needed in a ZK circuit. With RISC-V, the increased number of steps translates to longer traces and more constraints to prove.
MIPS is not theoretical - it powers systems like Optimism’s fraud proof VM and has a long history of deployment in critical software. While RISC-V has early traction in zkRollups, its deployment across security-critical infrastructure is still maturing and fragmented.
Denser instructions in MIPS32r2 lead to fewer trace rows, reducing the overall proving cost. RISC-V programs often require more steps for equivalent logic, increasing the number of rows that must be committed and verified in the zero-knowledge proof.
While each MIPS instruction may carry more individual circuit cost due to its complexity, the total number of instructions per program is lower. This results in lower cumulative overhead. RISC-V’s simpler opcodes require composing many operations to express high-level logic, which increases the total circuit area needed to represent a program.
Choosing MIPS32r2 was not the easy path, but it was the path that made sense for scaling verifiable computation. ZKM made the harder engineering decision so that developers building on zkMIPS inherit a more performant, consistent, and scalable foundation for zk execution.
Subscribe to the ZKM Blog to stay updated with the latest research by ZKM. If you have any questions about the article, you can contact the ZKM team on discord: discord.com/zkm
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